The present invention relates to digital electronic circuits and, more particularly, to a voltage level shifter circuit that receives an input signal and generates an output signal that is a level-shifted version of the input signal.
Generally speaking, components and nodes in digital logic circuits transition from one logic level to another during the operation of the circuit. These transitions typically are between a logical high state at some voltage above ground level, and a logical low state at ground level. Occasionally, different circuits operating at different logical high voltage levels are required to interface with one another thereby requiring the voltage level of one circuit to be shifted with respect to the voltage level of the other circuit. For example, the voltage in one circuit may have a logic high voltage level of 0.75V and the voltage in the other circuit may have a logic high voltage level of 1.32V. The first circuit has a voltage swing of zero to 0.75V and the second circuit has a voltage swing of zero to 1.32V. Level shifters provide the connection between two such circuits, shifting the level of the signals from the first voltage swing to the second voltage swing.
One conventional voltage level shifter is illustrated in FIG. 1. This circuit attempts to eliminate static current, i.e. leakage current, consumption using a feedback circuit and a pull-device. The circuit comprises a first CMOS inverter 100 having complementary MOSFETs P1 and N1, a second CMOS inverter 110 having complementary MOSFETs P2 and N2, a third CMOS inverter 120 with complementary MOSFETs P3 and N3, and a feedback unit 130 comprising P-type MOSFET Pfb, N-type MOSFET Nfb and pull up device Ppu 140.
Each of the first and second inverters 100, 110 receives an input signal at a voltage Vin at a first, lower voltage level VDDL. The first inverter 100 outputs the inverse of the input signal at a node 150, which is input to the third inverter 120. The third inverter 120 inverts the signal at node 150 and provides an output signal Vout at voltage level VDDH, where the logical state of Vout reflects that of Vin. Thus, Vout is a level-shifted version of Vin.
The output of the second inverter 110 also is the inverse of the input voltage Vin, at the lower voltage level VDDL. This is fed to the gate of device Nfb of feedback unit 130. Similarly, the voltage at node 150 is fed to the gate of the device Pfb of the feedback unit 130. The feedback unit 130 provides an output signal at node 170 that is used to drive the gate of pull-up device Ppu 140.
Typically, the digital voltage level shifter of FIG. 1 operates as the input voltage at Vin transitions between a logical high at the first voltage VDDL and a logical low at ground voltage where it is desired that the output voltage Vout reflects the logical state of Vin, but at the level shifted voltage, VDDH. In this circuit, the input voltage Vin is at a first, lower voltage VDDL and the output voltage is at a second, higher voltage VDDH. It is believed that improvements may be realized in reduction of leakage current when VIN rises to a logic high of VDDL. For instance, and analyzing the case when VIN rises to a logic high of VDRL, N1 turns on, but P1 initially does not completely turn off since the source of P1 is at a voltage level of VDDH. Thus, static current temporarily flows through PPU, P1, and N1. Given the nature of normal CMOS processes, N-channel FETs have approximately twice the current sinking and sourcing capability of identically-sized P-channel FETs. Additionally, the circuit of FIG. 1 has two P-channel FETs, P1 and PPU, connected in series, thereby further reducing the strength of P1 and PPO in comparison to N1. Therefore, N1 succeeds in pulling node 150 to ground. VIN also turns N2 on and P2 completely off (since the source of P2 is attached to VDDL), thus pulling node 160 to ground. With the gates of both PFB and NFB pulled low, node 170 is pulled up to VDDH volts, thereby shutting off PPU and eliminating the static current that previously flowed through PPU, P1, and N1, and terminating the drive fight between P1 and N1. Also, with node 150 being at ground, P3 is on, N3 is off, and VOUT is pulled up to VDDH, all in response to VIN rising to VDDL.
As VIN transitions to logical low, P1 goes on and N1 goes off, however, node 150 remains at logical low (ground) because in the previous cycle of operation (as described above), Ppu was switched off, thereby isolating node 150 from VDDH, at least temporarily.
Additionally, P2 goes on and N2 goes off, thereby pulling node 160 to logical high at VDDL. In turn, Nfb goes on and since node 150 is currently at ground, Pfb is on, which means a leakage path exists from VDDH to ground through Pfb and Nfb. Node 170 is being driven by Pfb to be pulled up to VDDH and by Nfb to be pulled to ground. Because Nfb is of a physically larger size in order to influence the voltage at node 170 as described above, the larger-sized device Nfb wins the drive fight eventually pulling node 170 to ground. Only then is node 150 pulled up to VDDH through Ppu and P1, thereby switching Pfb off and cutting off the leakage from VDDH through Pfb and Nfb to ground.
The above-described circuit operation is less than optimal because of the leakage current from VDDH to ground through Pfb and Nfb, which flows for a relatively long time which, in turn, requires the physical size of device Nfb to be relatively large. Additionally, the circuit of FIG. 1 takes a relatively long time for the output voltage to transition to ground in response to a corresponding transition on the input voltage. Accordingly, it would be advantageous to have a digital voltage level shifter that provides some improvement on the above problems.